Patent Search Results

1 7,490,327 System and method for programmatic distributed transaction commit prioritization mechanism
2 7,389,368 Inter-DSP signaling in a multiple DSP environment
3 7,386,831 Interactive collaborative facility for inspection and review of software products
4 7,313,796 Reciprocity and stabilization in dynamic resource reallocation among logically partitioned systems
5 7,296,269 Balancing loads among computing nodes where no task distributor servers all nodes and at least one node is served by two or more task distributors
6 7,251,814 Yield on multithreaded processors
7 7,219,331 Method and apparatus for lightweight support on set top box
8 7,206,798 Apparatus and method for programmable dual stage digital filter
9 7,181,744 System and method for transferring data between virtual machines or other computer entities
10 7,174,553 Increasing parallelism of function evaluation in a database
11 7,174,551 Multiple task wait system for use in a data warehouse environment
12 7,171,667 System and method for allocating resources based on locally and globally determined priorities
13 7,168,074 Runtime prediction framework for CPU intensive applications
14 7,159,221 Computer OS dispatcher operation with user controllable dedication
15 7,155,720 Dynamic task assignment in workflows
16 7,143,411 Capping processor utilization
17 7,140,018 Method of using a distinct flow of computational control as a reusable abstract data object
18 7,137,118 Data synchronization hardware primitive in an embedded symmetrical multiprocessor computer
19 7,137,115 Method for controlling multithreading
20 7,109,985 System and method for dynamically generating on-demand digital images
21 7,096,468 Programmer/feeder system task linking program
22 7,076,781 Resource reservation for large-scale job scheduling
23 7,069,559 System and method for monitoring software queuing applications
24 7,065,682 Method for monitoring tests run on a personal computer
25 6,347,352 Computer system having a plurality of bus agents coupled to bus requesters wherein each bus agent includes an internal arbiter that selects one of the bus requests
26 6,295,601 System and method using partial trap barrier instruction to provide trap barrier class-based selective stall of instruction processing pipeline
27 6,266,758 Alignment and ordering of vector elements for single instruction multiple data processing
28 6,240,509 Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculation
29 6,233,672 Piping rounding mode bits with floating point instructions to eliminate serialization
30 6,233,671 Staggering execution of an instruction by dividing a full-width macro instruction into at least two partial-width micro instructions
31 6,223,265 Single-chip microcomputer synchronously controlling external synchronous memory responsive to memory clock signal and clock enable signal
32 6,219,777 Register file having shared and local data word parts
33 6,219,716 System for bidirectional transfer of concurrently compressed divided groups of data to be distributed, concurrently expanded, and combined using unique data group identifiers
34 6,212,620 Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals
35 6,212,619 System and method for high-speed register renaming by counting
36 6,212,590 Computer system having integrated bus bridge design with delayed transaction arbitration mechanism employed within laptop computer docked to expansion base
37 6,212,559 Automated configuration of internet-like computer networks
38 6,209,022 Slave station with two output circuits commonly and directly connected to a line for serially transmitting data to a master station in two operational modes
39 6,205,520 Method and apparatus for implementing non-temporal stores
40 6,205,468 System for multitasking management employing context controller having event vector selection by priority encoding of contex events
41 6,202,143 System for fetching unit instructions and multi instructions from memories of different bit widths and converting unit instructions to multi instructions by adding NOP instructions
42 6,202,105 Host adapter capable of simultaneously transmitting and receiving data of multiple contexts between a computer bus and peripheral bus
43 6,199,132 Communication link with isochronous and asynchronous priority modes
44 6,195,753 Information processing apparatus with reduced power consumption
45 6,195,747 System and method for reducing data traffic between a processor and a system controller in a data processing system
46 6,195,741 Data processing device having a variable length code processing mechanism
47 6,195,733 Method to share memory in a single chip multiprocessor system
48 6,195,716 System bus interface controlling at least one slave device by exchanging three control signals
49 6,192,465 Using multiple decoders and a reorder queue to decode instructions out of order
50 6,192,384 System and method for performing compound vector operations