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| 1 |
7,523,296 |
System and method for handling exceptions and branch mispredictions in a
superscalar microprocessor
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| 2 |
7,383,426 |
Processor employing loadable configuration parameters to reduce or
eliminate setup and pipeline delays in a pipeline system
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| 3 |
7,380,112 |
Processor and compiler for decoding an instruction and executing the
decoded instruction with conditional execution flags
|
| 4 |
7,366,879 |
Alteration of functional unit partitioning scheme in multithreaded
processor based upon thread statuses
|
| 5 |
7,360,070 |
Specialized processing upon an occurrence of an exceptional situation
during the course of a computation
|
| 6 |
7,360,060 |
Using IMPDEP2 for system commands related to Java accelerator hardware
|
| 7 |
7,353,364 |
Apparatus and method for sharing a functional unit execution resource
among a plurality of functional units
|
| 8 |
7,350,054 |
Processor having array of processing elements whose individual operations
and mutual connections are variable
|
| 9 |
7,343,478 |
Register window system and method that stores the next register window in
a temporary buffer
|
| 10 |
7,343,474 |
Minimal address state in a fine grain multithreaded processor
|
| 11 |
7,343,472 |
Processor having a finite field arithmetic unit utilizing an array of
multipliers and adders
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| 12 |
7,334,116 |
Bit manipulation on data in a bitstream that is stored in a memory having
an address boundary length
|
| 13 |
7,334,110 |
Decoupled scalar/vector computer architecture system and method
|
| 14 |
7,334,009 |
Microprocessor with random number generator and instruction for storing
random data
|
| 15 |
7,331,041 |
Method of changing modes of code generation
|
| 16 |
7,321,964 |
Store-to-load forwarding buffer using indexed lookup
|
| 17 |
7,313,677 |
Processing activity masking in a data processing system
|
| 18 |
7,305,543 |
Memory organization allowing single cycle pointer addressing where the
address of the pointer is also contained in one of the memory locations
|
| 19 |
7,302,552 |
System for processing VLIW words containing variable length instructions
having embedded instruction length identifiers
|
| 20 |
7,296,141 |
Method for cancelling speculative conditional delay slot instructions
|
| 21 |
7,281,120 |
Apparatus and method for decreasing the latency between an instruction
cache and a pipeline processor
|
| 22 |
7,272,700 |
Methods and apparatus for indirect compound VLIW execution using operand
address mapping techniques
|
| 23 |
7,263,603 |
Method and apparatus for avoiding read-after-write hazards in an
execute-ahead processor
|
| 24 |
7,257,697 |
Processing system with general purpose execution unit and separate
independently operating data string manipulation unit
|
| 25 |
7,237,087 |
Reconfigurable multidimensional array processor allowing runtime
reconfiguration of selected individual array cells
|
| 26 |
7,219,112 |
Microprocessor with instruction translator for translating an instruction
for storing random data bytes
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| 27 |
7,216,219 |
Method and apparatus for avoiding write-after-read hazards in an
execute-ahead processor
|
| 28 |
7,213,133 |
Method and apparatus for avoiding write-after-write hazards in an
execute-ahead processor
|
| 29 |
7,206,926 |
Programmable unit including program operation unit and associated stopping
device
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| 30 |
7,155,599 |
Method and apparatus for a register renaming structure
|
| 31 |
7,149,878 |
Changing instruction set architecture mode by comparison of current
instruction execution address with boundary address register values
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| 32 |
7,143,266 |
Storing immediate data of immediate instructions in a data table
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| 33 |
7,139,899 |
Selected register decode values for pipeline stage register addressing
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| 34 |
7,139,897 |
Computer instruction dispatch
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| 35 |
7,136,991 |
Microprocessor including random number generator supporting operating
system-independent multitasking operation
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| 36 |
7,117,346 |
Data processing system having multiple register contexts and method
therefor
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| 37 |
7,114,060 |
Selectively deferring instructions issued in program order utilizing a
checkpoint and multiple deferral scheme
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| 38 |
7,065,633 |
System for delivering exception raised in first architecture to operating
system coded in second architecture in dual architecture CPU
|
| 39 |
RE39,121 |
Processor which can favorably execute a rounding process composed of
positive conversion and saturated calculation processing
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| 40 |
7,047,399 |
Computer system and method for fetching, decoding and executing
instructions
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| 41 |
7,047,394 |
Computer for execution of RISC and CISC instruction sets
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| 42 |
7,039,790 |
Very long instruction word microprocessor with execution packet spanning
two or more fetch packets with pre-dispatch instruction selection from
two latches according to instruction bit
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| 43 |
7,028,171 |
Multi-way select instructions using accumulated condition codes
|
| 44 |
7,024,541 |
Register window spill technique for retirement window having entry size
less than amount of spill instructions
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| 45 |
7,013,353 |
Host-fabric adapter having an efficient multi-tasking pipelined
instruction execution micro-controller subsystem
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| 46 |
6,990,658 |
Method for translating instructions in a speculative microprocessor
featuring committing state
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| 47 |
6,976,152 |
Comparing operands of instructions against a replay scoreboard to detect an
instruction replay and copying a replay scoreboard to an issue scoreboard
|
| 48 |
6,976,150 |
Resource flow computing device
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| 49 |
6,920,548 |
System and method for retiring approximately simultaneously a group of
instructions in a superscalar microprocessor
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| 50 |
6,915,410 |
Compiler synchronized multi-processor programmable logic device with direct
transfer of computation results among processors
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