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| 1 |
7,430,629 |
Internet SCSI communication via UNDI services
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| 2 |
7,424,560 |
Universal serial bus hub with wireless communication to remote peripheral
devices
|
| 3 |
7,415,556 |
Exclusion control
|
| 4 |
7,392,336 |
Connecting device of storage device and computer system including the same
connecting device
|
| 5 |
7,386,649 |
Multiple processor system and method including multiple memory hub modules
|
| 6 |
7,380,033 |
Communication apparatus implementing time domain isolation with restricted
bus access
|
| 7 |
7,373,446 |
Method and system for dynamically patching an operating system's interrupt
mechanism
|
| 8 |
7,366,808 |
System, method and apparatus for multiple-protocol-accessible OSD storage
subsystem
|
| 9 |
7,363,401 |
Method and apparatus for controlling bus transactions depending on bus
clock frequency
|
| 10 |
7,363,400 |
Data transfer switch
|
| 11 |
7,360,007 |
System including a segmentable, shared bus
|
| 12 |
7,350,014 |
Connecting peer endpoints
|
| 13 |
7,350,004 |
Resource management device
|
| 14 |
7,350,003 |
Method, system, and apparatus for an adaptive weighted arbiter
|
| 15 |
7,350,002 |
Round-robin bus protocol
|
| 16 |
7,346,729 |
Peripherals of computer
|
| 17 |
7,346,724 |
Enabling multiple ATA devices using a single bus bridge
|
| 18 |
7,346,722 |
Apparatus for use in a computer systems
|
| 19 |
7,346,720 |
Systems and methods for managing concurrent access requests to a shared
resource
|
| 20 |
7,346,719 |
Systems, methods, and bus controllers for creating an event trigger on a
network bus
|
| 21 |
7,343,441 |
Method and apparatus of remote computer management
|
| 22 |
7,340,555 |
RAID system for performing efficient mirrored posted-write operations
|
| 23 |
7,340,552 |
Bus control system
|
| 24 |
7,340,547 |
Servicing of multiple interrupts using a deferred procedure call in a
multiprocessor system
|
| 25 |
7,337,259 |
Smart card virtual hub
|
| 26 |
7,337,254 |
Information processing system and method of controlling the same
|
| 27 |
7,337,253 |
Method and system of routing network-based data using frame address
notification
|
| 28 |
7,334,074 |
Method and system for multi-channel transfer of data and control
|
| 29 |
7,334,070 |
Multi-channel memory architecture for daisy chained arrangements of nodes
with bridging between memory channels
|
| 30 |
7,330,926 |
Interruption control system
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| 31 |
7,330,923 |
Input devices and methods of operating same
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| 32 |
7,330,921 |
Communication control circuit and communication control method
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| 33 |
7,328,295 |
Interrupt controller and interrupt controlling method for prioritizing
interrupt requests generated by a plurality of interrupt sources
|
| 34 |
7,328,291 |
System and method for controlling the service engagement in a data bus
system
|
| 35 |
7,328,290 |
System and method of automatically switching control of a bus in a
processor-based device
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| 36 |
7,328,289 |
Communication between processors
|
| 37 |
7,325,082 |
System and method for guaranteeing transactional fairness among multiple
requesters
|
| 38 |
7,321,945 |
Interrupt control device sending data to a processor at an optimized time
|
| 39 |
7,315,913 |
CPU system, bus bridge, control method therefor, and computer system
|
| 40 |
7,315,911 |
Method for efficient inter-processor communication in an active-active
RAID system using PCI-express links
|
| 41 |
7,315,910 |
Techniques for handling lock-related inconsistencies
|
| 42 |
7,310,697 |
System and method for dynamic USB power source
|
| 43 |
7,308,522 |
Method and apparatus to allow dynamic variation of ordering enforcement
between transactions in a strongly ordered computer interconnect
|
| 44 |
7,305,588 |
Testing the interrupt sources of a microprocessor
|
| 45 |
7,305,507 |
Multi-stage round robin arbitration system
|
| 46 |
7,302,507 |
Reestablishing connections when a block/device at one end is
re-initialized
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| 47 |
7,296,106 |
Centerplaneless computer system
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| 48 |
7,290,072 |
Protocols and standards for USB peripheral communications
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| 49 |
7,287,111 |
Method and system for creating and dynamically selecting an arbiter design
in a data processing system
|
| 50 |
7,287,108 |
Capacitive multidrop bus compensation
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