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| 1 |
8,293,547 |
Hybrid integrated circuit device
|
| 2 |
8,218,277 |
Shared electrostatic discharge protection for integrated circuit output
drivers
|
| 3 |
8,181,140 |
T-coil network design for improved bandwidth and electrostatic discharge
immunity
|
| 4 |
8,174,112 |
Integrated circuit device with low capacitance and high thermal
conductivity interface
|
| 5 |
8,134,813 |
Method and apparatus to reduce footprint of ESD protection within an
integrated circuit
|
| 6 |
8,079,002 |
Method and apparatus for evaluating paths in an integrated circuit design
|
| 7 |
7,947,980 |
Non-volatile memory cell with charge storage element and method of
programming
|
| 8 |
7,919,845 |
Formation of a hybrid integrated circuit device
|
| 9 |
7,812,674 |
Common centroid electrostatic discharge protection for integrated circuit
devices
|
| 10 |
7,812,642 |
Pass gate with improved latchup immunity
|
| 11 |
7,687,797 |
Three-terminal non-volatile memory element with hybrid gate dielectric
|
| 12 |
7,544,968 |
Non-volatile memory cell with charge storage element and method of
programming
|
| 13 |
7,450,431 |
PMOS three-terminal non-volatile memory element and method of programming
|
| 14 |
7,420,842 |
Method of programming a three-terminal non-volatile memory element using
source-drain bias
|
| 15 |
7,002,219 |
Electrical fuse for integrated circuits
|
| 16 |
6,740,936 |
Ballast resistor with reduced area for ESD protection
|
| 17 |
6,638,852 |
Structure and method for preventing barrier failure
|
| 18 |
6,549,458 |
Non-volatile memory array using gate breakdown structures
|
| 19 |
6,522,582 |
Non-volatile memory array using gate breakdown structures
|
| 20 |
6,432,808 |
Method of improved bondability when using fluorinated silicon glass
|
| 21 |
6,316,132 |
Structure and method for preventing barrier failure
|
| 22 |
6,266,269 |
Three terminal non-volatile memory element
|
| 23 |
6,044,012 |
Non-volatile memory array using gate breakdown structure in standard sub
0.35 micron CMOS process
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